A novel static prediction scheme for filter cache structures

K Vivekanandarajah, T Srikanthan, C T Clarke, S Bhattacharyya

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Energy dissipation in cache memories is becoming a major design issue for embedded microprocessors. Predictive filter cache based instruction cache hierarchy has been shown to effectively reduce the energy-delay product. In this paper, a simplified pattern prediction algorithm is proposed for the filter cache hierarchy. The prediction scheme relies on the static nature of the hit or miss pattern of the instruction access streams. The static patterns are maintained in a small 32x1-bit wide Static Pattern Table (SPT). Our investigations show that the proposed prediction algorithm is superior to that based on Next Fetch Prediction Table (NFPT) for all the benchmarks simulated. With the proposed approach, energy delay product reduction of up to 6.79% was evident when compared with that using NFPT. Moreover, since the prediction scheme is based on the static assignment of patterns, it lends well for area and power efficient implementation than that employs dynamic pattern prediction although it is marginally inferior (i.e. 0.69%) in term of energy delay product.
Original languageEnglish
Pages (from-to)543-548
Number of pages6
JournalIEICE Transactions on Electronics
VolumeE87C
Issue number4
Publication statusPublished - 2004

Fingerprint

Cache memory
Microprocessor chips
Energy dissipation

Cite this

Vivekanandarajah, K., Srikanthan, T., Clarke, C. T., & Bhattacharyya, S. (2004). A novel static prediction scheme for filter cache structures. IEICE Transactions on Electronics, E87C(4), 543-548.

A novel static prediction scheme for filter cache structures. / Vivekanandarajah, K; Srikanthan, T; Clarke, C T; Bhattacharyya, S.

In: IEICE Transactions on Electronics, Vol. E87C, No. 4, 2004, p. 543-548.

Research output: Contribution to journalArticle

Vivekanandarajah, K, Srikanthan, T, Clarke, CT & Bhattacharyya, S 2004, 'A novel static prediction scheme for filter cache structures', IEICE Transactions on Electronics, vol. E87C, no. 4, pp. 543-548.
Vivekanandarajah K, Srikanthan T, Clarke CT, Bhattacharyya S. A novel static prediction scheme for filter cache structures. IEICE Transactions on Electronics. 2004;E87C(4):543-548.
Vivekanandarajah, K ; Srikanthan, T ; Clarke, C T ; Bhattacharyya, S. / A novel static prediction scheme for filter cache structures. In: IEICE Transactions on Electronics. 2004 ; Vol. E87C, No. 4. pp. 543-548.
@article{057b8f145e52497588ad670c183b83a0,
title = "A novel static prediction scheme for filter cache structures",
abstract = "Energy dissipation in cache memories is becoming a major design issue for embedded microprocessors. Predictive filter cache based instruction cache hierarchy has been shown to effectively reduce the energy-delay product. In this paper, a simplified pattern prediction algorithm is proposed for the filter cache hierarchy. The prediction scheme relies on the static nature of the hit or miss pattern of the instruction access streams. The static patterns are maintained in a small 32x1-bit wide Static Pattern Table (SPT). Our investigations show that the proposed prediction algorithm is superior to that based on Next Fetch Prediction Table (NFPT) for all the benchmarks simulated. With the proposed approach, energy delay product reduction of up to 6.79{\%} was evident when compared with that using NFPT. Moreover, since the prediction scheme is based on the static assignment of patterns, it lends well for area and power efficient implementation than that employs dynamic pattern prediction although it is marginally inferior (i.e. 0.69{\%}) in term of energy delay product.",
author = "K Vivekanandarajah and T Srikanthan and Clarke, {C T} and S Bhattacharyya",
note = "ID number: ISI:000220778100015",
year = "2004",
language = "English",
volume = "E87C",
pages = "543--548",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "4",

}

TY - JOUR

T1 - A novel static prediction scheme for filter cache structures

AU - Vivekanandarajah, K

AU - Srikanthan, T

AU - Clarke, C T

AU - Bhattacharyya, S

N1 - ID number: ISI:000220778100015

PY - 2004

Y1 - 2004

N2 - Energy dissipation in cache memories is becoming a major design issue for embedded microprocessors. Predictive filter cache based instruction cache hierarchy has been shown to effectively reduce the energy-delay product. In this paper, a simplified pattern prediction algorithm is proposed for the filter cache hierarchy. The prediction scheme relies on the static nature of the hit or miss pattern of the instruction access streams. The static patterns are maintained in a small 32x1-bit wide Static Pattern Table (SPT). Our investigations show that the proposed prediction algorithm is superior to that based on Next Fetch Prediction Table (NFPT) for all the benchmarks simulated. With the proposed approach, energy delay product reduction of up to 6.79% was evident when compared with that using NFPT. Moreover, since the prediction scheme is based on the static assignment of patterns, it lends well for area and power efficient implementation than that employs dynamic pattern prediction although it is marginally inferior (i.e. 0.69%) in term of energy delay product.

AB - Energy dissipation in cache memories is becoming a major design issue for embedded microprocessors. Predictive filter cache based instruction cache hierarchy has been shown to effectively reduce the energy-delay product. In this paper, a simplified pattern prediction algorithm is proposed for the filter cache hierarchy. The prediction scheme relies on the static nature of the hit or miss pattern of the instruction access streams. The static patterns are maintained in a small 32x1-bit wide Static Pattern Table (SPT). Our investigations show that the proposed prediction algorithm is superior to that based on Next Fetch Prediction Table (NFPT) for all the benchmarks simulated. With the proposed approach, energy delay product reduction of up to 6.79% was evident when compared with that using NFPT. Moreover, since the prediction scheme is based on the static assignment of patterns, it lends well for area and power efficient implementation than that employs dynamic pattern prediction although it is marginally inferior (i.e. 0.69%) in term of energy delay product.

M3 - Article

VL - E87C

SP - 543

EP - 548

JO - IEICE Transactions on Electronics

JF - IEICE Transactions on Electronics

SN - 0916-8524

IS - 4

ER -