A 1.2 V low-power OpAmp for integrated lock-in amplifiers

M. R. Valero; S. Celma; N. Medrano; B. Calvo; C. Gimeno

doi:10.1117/12.2017218

A 1.2 V low-power OpAmp for integrated lock-in amplifiers

M. R. Valero, S. Celma, N. Medrano, B. Calvo, C. Gimeno

Department of Electronic & Electrical Engineering

University of Zaragoza

Research output: Chapter or section in a book/report/conference proceeding › Chapter in a published conference proceeding

1 Citation (SciVal)

Abstract

This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.

Original language	English
Title of host publication	VLSI Circuits and Systems VI: Proceedings
Publisher	SPIE
Volume	8764
ISBN (Print)	9780819495617
DOIs	https://doi.org/10.1117/12.2017218
Publication status	Published - 12 Aug 2013
Event	6th Conference on VLSI Circuits and Systems - Grenoble, France Duration: 24 Apr 2013 → 26 Apr 2013

Conference

Conference	6th Conference on VLSI Circuits and Systems
Country/Territory	France
City	Grenoble
Period	24/04/13 → 26/04/13

Keywords

Amplifiers
Analog circuits
CMOS integrated circuits
Lock-in amplifiers
Low-voltage low-power design

ASJC Scopus subject areas

Electronic, Optical and Magnetic Materials
Condensed Matter Physics
Computer Science Applications
Applied Mathematics
Electrical and Electronic Engineering

Access to Document

10.1117/12.2017218

Cite this

@inproceedings{535de78414fa4a1f9c33c55edafcffec,

title = "A 1.2 V low-power OpAmp for integrated lock-in amplifiers",

abstract = "This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.",

keywords = "Amplifiers, Analog circuits, CMOS integrated circuits, Lock-in amplifiers, Low-voltage low-power design",

author = "Valero, {M. R.} and S. Celma and N. Medrano and B. Calvo and C. Gimeno",

year = "2013",

month = aug,

day = "12",

doi = "10.1117/12.2017218",

language = "English",

isbn = "9780819495617",

volume = "8764",

booktitle = "VLSI Circuits and Systems VI: Proceedings",

publisher = "SPIE",

address = "USA United States",

note = "6th Conference on VLSI Circuits and Systems ; Conference date: 24-04-2013 Through 26-04-2013",

}

TY - GEN

T1 - A 1.2 V low-power OpAmp for integrated lock-in amplifiers

AU - Valero, M. R.

AU - Celma, S.

AU - Medrano, N.

AU - Calvo, B.

AU - Gimeno, C.

PY - 2013/8/12

Y1 - 2013/8/12

N2 - This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.

AB - This paper presents a simple 1.2 V low-power rail-to-rail class AB operational amplifier (OpAmp) suitable for integrated lock-in amplifiers. The proposed OpAmp has been designed in a standard 0.18 μm CMOS technology. For a 1.2 V single supply and 68.6 μW power consumption, simulations shows a 81 dB open loop gain, 64° phase margin, 13 MHz unity gain frequency for a capacitive load of 10pF and 75 dB CMRR. Adaptive biasing provides 30.7 V/μs slew-rate for a 10 pF load. A compact and reliable lock-in amplifier (LIA) has been designed using the proposed circuit. The designed LIA has a power consumption of 135 μW and recovers signals up to 1 MHz with relative errors below 2.6 % for noise and interference signals of the same amplitude as the signal of interest.

KW - Amplifiers

KW - Analog circuits

KW - CMOS integrated circuits

KW - Lock-in amplifiers

KW - Low-voltage low-power design

UR - http://www.scopus.com/inward/record.url?scp=84881124770&partnerID=8YFLogxK

U2 - 10.1117/12.2017218

DO - 10.1117/12.2017218

M3 - Chapter in a published conference proceeding

AN - SCOPUS:84881124770

SN - 9780819495617

VL - 8764

BT - VLSI Circuits and Systems VI: Proceedings

PB - SPIE

T2 - 6th Conference on VLSI Circuits and Systems

Y2 - 24 April 2013 through 26 April 2013

ER -

A 1.2 V low-power OpAmp for integrated lock-in amplifiers

Abstract

Conference

Keywords

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this