A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder

Andreas Demosthenous, John Taylor

Research output: Contribution to journalArticle

25 Citations (Scopus)

Abstract

his paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in
0.8-m CMOS technology. Although analog implementations have been described in the
literature, this decoder is the first to be reported realizing the add–compare–select section
entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel
rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate
of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable ...
Original languageEnglish
Pages (from-to)904-910
Number of pages7
JournalIEEE Journal of Solid-State Circuits
Volume37
Issue number7
DOIs
Publication statusPublished - Jul 2002

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Analog circuits
Electric power utilization

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A 100-Mb/s 2.8-V CMOS current-mode analog Viterbi decoder. / Demosthenous, Andreas; Taylor, John.

In: IEEE Journal of Solid-State Circuits, Vol. 37, No. 7, 07.2002, p. 904-910.

Research output: Contribution to journalArticle

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