Abstract
his paper describes a 4-state rate-1/2 analog convolutional decoder fabricated in
0.8-m CMOS technology. Although analog implementations have been described in the
literature, this decoder is the first to be reported realizing the add–compare–select section
entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel
rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate
of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable ...
0.8-m CMOS technology. Although analog implementations have been described in the
literature, this decoder is the first to be reported realizing the add–compare–select section
entirely with current-mode analog circuits. It operates at data rates up to 115 Mb/s (channel
rate 230 Mb/s) and consumes 39 mW at that rate from a single 2.8-V power supply. At a rate
of 100 Mb/s, the power consumption per trellis state is about 1/3 that of a comparable ...
| Original language | English |
|---|---|
| Pages (from-to) | 904-910 |
| Number of pages | 7 |
| Journal | IEEE Journal of Solid-State Circuits |
| Volume | 37 |
| Issue number | 7 |
| DOIs | |
| Publication status | Published - Jul 2002 |